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t november 1998 american microsystems, inc. reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. 11.20.98 )6 )lyh3//&orfn*hqhudwru,& ,62 1.0 features five phase-locked loops (plls) generate five inde- pendent clocks from one reference clock three pll frequencies can be changed via logic level on the sel input clock outputs can be tristated to facilitate circuit board testing small circuit board footprint (16-pin 0.150 2 soic) custom frequency selections available C contact your local ami sales representative for more information 2.0 description the fs6017 is a monolithic cmos clock generator ic designed to minimize cost and component count in net- work computer applications. five internal high-performance phase-locked loops use an on-chip crystal oscillator as a reference for generation of various frequencies. the pll-generated clock fre- quencies are related to the crystal oscillator frequency by exact ratios. 3.0 applications frequency synthesis network computer (nc), fast network computer, and thin client applications figure 1: pin configuration 1 16 2 3 4 5 6 7 8 15 14 13 12 11 10 9 vss clk1 oe vss xin xout sel vdd vdd clkd vss clkc clk2 vdd clkb ref fs6017 16-pin 0.150 2 soic figure 2: block diagram pll b reference oscillator sel oe fs6017 clkb pll 1 xout xin clk2 clk1 pll 2 pll c clkc pll d clkd ref
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t november 1998 11.20.98 2 )6 )lyh3//&orfn*hqhudwru,& ,62 table 1: pin descriptions key: ai = analog input; ao = analog output; di = digital input; di u = input with internal pull-up; di d = input with internal pull-down; dio = digital input/output; di-3 = three-level digital input, do = digital output; p = power/ground; # = active low pin pin type name description 1 p vss crystal oscillator ground 2 do clk1 pll 1 clock output 3di u oe output enable 4 p vss ground 5 ai xin crystal oscillator feedback 6 ao xout crystal oscillator drive 7di u sel output frequency select 8 p vdd power supply (+5v) 9 p vdd crystal oscillator power (+5v) 10 do clkd pll d clock output 11 p vss ground 12 do clkc pll c clock output 13 do clk2 pll 2 clock output 14 p vdd power supply (+5v) 15 do clkb pll b clock output 16 do ref reference oscillator output 4.0 functional block description 4.1 phase-locked loops (plls) each one of the five on-chip plls in the fs6017 is a standard frequency- and phase-locked loop architecture. each pll multiplies the reference oscillator to the desired frequency by a ratio of integers. the frequency multipli- cation is exact. 4.2 frequency select (sel) three of the plls can switch between one of two possi- ble output frequencies depending on the logic state of the sel pin. the clock outputs that can be changed are the clkb, clkc, and clkd outputs. note that the transi- tions are not glitch-free. the sel pin defaults to a logic-high through an internal pull-up. table 2: output frequencies output clock sel pin frequency (mhz) clk1 - 11.2896 clk2 - 32.0000 1 56.0000 clkb 0 64.0000 1 40.0000 clkc 0 48.0000 1 80.0000 clkd 0 3.6864 note: custom frequencies available C contact ami for more information 4.3 output tristate control (oe) all clock outputs of the fs6017 may be tristated to facili- tate circuit board testing. when the output enable (oe) pin is low, all outputs are placed in a high-impedance state and the outputs can neither drive nor load con- nected lines. by default, all the clock outputs are enabled through an internal pull-up on the oe pin.
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t november 1998 11.20.98 3 )6 )lyh3//&orfn*hqhudwru,& ,62 4.4 crystal oscillator an on-board 24mhz crystal oscillator provides the refer- ence frequency for all five plls. loading capacitors are left external to allow the user to vary crystal types and frequencies. the oscillator operates the crystal in a parallel-resonant mode. series-resonant crystals can also be used with the fs6017, although the oscillation frequency will be slightly higher than the frequency that is stamped on the can (typically 0.025 to 0.05%) since the entire operation of the fs6017 depends on having a stable reference frequency, the crystal should be mounted as close as possible to the package. take care to avoid routing clock lines near the crystal and, if possible, ground the crystal can to the ground plane. the output of the crystal oscillator is directly observable at the ref output. 5.0 electrical specifications table 3: absolute maximum ratings stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these conditions represent a stress rating only, and functional operation of the device at these or any other conditions above the operational limits noted in this specification is not implied. exposure to maximum rati ng conditions for extended conditions may affect device performance, functionality, and reliability. parameter symbol min. max. units supply voltage, dc (v ss = ground) v dd v ss -0.5 7 v input voltage, dc v i v ss -0.5 v dd +0.5 v output voltage, dc v o v ss -0.5 v dd +0.5 v input clamp current, dc (v i < 0 or v i > v dd )i ik -50 50 ma output clamp current, dc (v i < 0 or v i > v dd )i ok -50 50 ma storage temperature range (non-condensing) t s -65 150 c ambient temperature range, under bias t a -55 125 c junction temperature t j 150 c lead temperature (soldering, 10s) 260 c input static discharge voltage protection (mil-std 883e, method 3015.7) 2 kv caution: electrostatic sensitive device permanent damage resulting in a loss of functionality or performance may occur if this device is subjected to a high-energy ele c- trostatic discharge. table 4: operating conditions parameter symbol conditions/description min. typ. max. units supply voltage v dd 5v 10% 4.5 5 5.5 v ambient operating temperature range t a 070c output load capacitance c l 15 pf crystal resonator frequency f xin 527mhz crystal resonator load capacitance c xtal assumes 6pf external load capacitance typically achieved with 12pf from xin to vss and 12pf from xout to vss 15 pf crystal resonator motional capacitance c mot 25 ff
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t november 1998 11.20.98 4 )6 )lyh3//&orfn*hqhudwru,& ,62 table 5: dc electrical specifications unless otherwise stated, v dd = 5.0v 10%, no load on any output, and ambient temperature range t a = 0c to 70c. parameters denoted with an asterisk ( * ) represent nominal characterization data and are not production tested to any specific limits. where given, min and max characterization data are 3 s from typical. negative currents indicate current flows out of the device. parameter symbol conditions/description min. typ. max. units overall supply current, dynamic, with loaded outputs * i dd oe = sel = 5.0v 80 ma supply current, dynamic, with tristated outputs i dd oe = 0v 55 80 ma control inputs (sel, oe) high-level input voltage v ih 2.4 v dd +0.3 v low-level input voltage v il v ss -0.3 0.8 v high-level input current i ih -1 1 m a low-level input current (pull-up) i il outputs off; v il = 0v, v dd = 5.5v 2 3.8 10 m a crystal oscillator feedback (xin) threshold bias voltage v th 1.5 2.4 3.5 v high-level input current i ih v dd = v i = 5.5v 55 83 100 m a low-level input current i il v dd = 5.5v; v i = 0v -55 -81 -100 m a crystal loading capacitance * c l(xtal) as seen by an external crystal connected to xin and xout (see table 4) 9pf input loading capacitance * c l(xin) as seen by an external clock driver on xin; xout unconnected 18 pf crystal oscillator drive (xout) high-level output source current i oh v dd = 5.5v, v o = 0v -10 -19 -33 ma low-level output sink current i ol v dd = v o = 5.5v 10 26 33 ma clock outputs (clk1, clk2, clkb, clkc, clkd, ref) high-level output source current i oh v o = 2.4v -26 -37 ma low-level output sink current i ol v o = 0.4v 7 9.2 ma z oh v o = 0.5v dd ; output driving high 57 output impedance z ol v o = 0.5v dd ; output driving low 52 w tristate output current i z -10 10 m a short circuit source current * i sch v o = 0v; shorted for 30s, max. -50 ma short circuit sink current * i scl v o = 5v; shorted for 30s, max. 55 ma
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t november 1998 11.20.98 5 )6 )lyh3//&orfn*hqhudwru,& ,62 table 6: ac timing specifications unless otherwise stated, v dd = 5.0v 10%, no load on any output, and ambient temperature range t a = 0c to 70c. parameters denoted with an asterisk ( * ) represent nominal characterization data and are not production tested to any specific limits. where given, min and max characterization data are 3 s from typical. parameter symbol conditions/description clock (mhz) min. typ. max. units clock output (ref) duty cycle * from rising edge to rising edge at 2.5v 24.000 50 54 % jitter, long term ( s y 2 ( t )) * t j(lt) from rising edge to 1st rising edge after 500 m s at 2.5v, c l = 15pf, all plls active 24.000 1000 ps jitter, period (peak-peak) * t j( d p) from rising edge to the next rising edge at 2.5v, c l = 15pf, all plls active 24.000 1440 ps rise time * t r v o = 0.5v to 4.5v; c l = 15pf 3.1 ns fall time * t f v o = 4.5v to 0.5v; c l = 15pf 1.2 ns clock output (clk1) duty cycle * from rising edge to rising edge at 2.5v 32.000 46 50 % jitter, long term ( s y 2 ( t )) * t j(lt) from rising edge to 1st rising edge after 500 m s at 2.5v, c l = 15pf, all plls active 32.000 490 ps jitter, period (peak-peak) * t j( d p) from rising edge to the next rising edge at 2.5v, c l = 15pf, all plls active 32.000 1690 ps rise time * t r v o = 0.5v to 4.5v; c l = 15pf 3.2 ns fall time * t f v o = 4.5v to 0.5v; c l = 15pf 2.0 ns clock stabilization time * t stb from power-up to output active 1.3 ms clock output (clk2) duty cycle * from rising edge to rising edge at 2.5v 11.289 43 47 % jitter, long term ( s y 2 ( t )) * t j(lt) from rising edge to 1st rising edge after 500 m s at 2.5v, c l = 15pf, all plls active 11.289 840 ps jitter, period (peak-peak) * t j( d p) from rising edge to the next rising edge at 2.5v, c l = 15pf, all plls active 11.289 2900 ps rise time * t r v o = 0.5v to 4.5v; c l = 15pf 4.0 ns fall time * t f v o = 4.5v to 0.5v; c l = 15pf 2.1 ns clock stabilization time * t stb from power-up to output active 1.3 ms clock output (clkb) 56.000 39 43 duty cycle * from rising edge to rising edge at 2.5v 64.000 38 42 % 56.000 1350 jitter, long term ( s y 2 ( t )) * t j(lt) from rising edge to 1st rising edge after 500 m s at 2.5v, c l = 15pf, all plls active 64.000 1760 ps 56.000 1990 jitter, period (peak-peak) * t j( d p) from rising edge to the next rising edge at 2.5v, c l = 15pf, all plls active 64.000 1950 ps rise time * t r v o = 0.5v to 4.5v; c l = 15pf 3.1 ns fall time * t f v o = 4.5v to 0.5v; c l = 15pf 1.6 ns clock stabilization time * t stb from power-up to output active 1.5 ms
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t november 1998 11.20.98 6 )6 )lyh3//&orfn*hqhudwru,& ,62 table 7: ac timing specifications, continued unless otherwise stated, v dd = 5.0v 10%, no load on any output, and ambient temperature range t a = 0c to 70c. parameters denoted with an asterisk ( * ) represent nominal characterization data and are not production tested to any specific limits. where given, min and max characterization data are 3 s from typical. parameter symbol conditions/description clock (mhz) min. typ. max. units clock output (clkc) 40.000 43 47 duty cycle * from rising edge to rising edge at 2.5v 48.000 42 46 % 40.000 1550 jitter, long term ( s y 2 ( t )) * t j(lt) from rising edge to 1st rising edge after 500 m s at 2.5v, c l = 15pf, all plls active 48.000 2070 ps 40.000 1530 jitter, period (peak-peak) * t j( d p) from rising edge to the next rising edge at 2.5v, c l = 15pf, all plls active 48.000 2720 ps rise time * t r v o = 0.5v to 4.5v; c l = 15pf 3.0 ns fall time * t f v o = 4.5v to 0.5v; c l = 15pf 2.3 ns clock stabilization time * t stb from power-up to output active 1.3 ms clock output (clkd) 80.000 39 43 duty cycle * from rising edge to rising edge at 2.5v 3.686 48 52 % 80.000 1260 jitter, long term ( s y 2 ( t )) * t j(lt) from rising edge to 1st rising edge after 500 m s at 2.5v, c l = 15pf, all plls active 3.686 1620 ps rise time * t r v o = 0.5v to 4.5v; c l = 15pf 2.7 ns fall time * t f v o = 4.5v to 0.5v; c l = 15pf 1.3 ns clock stabilization time * t stb from power-up to output active 1.9 ms figure 3: clk1, clk2, clkb, clkc, clkd, ref clock outputs low drive current (ma) high drive current (ma) voltage (v) min. typ. max. voltage (v) min. typ. max. 0 0 0 0 0 -35 -60 -89 0.2 4 5 6 0.5 -34 -59 -87 0.5 9 13 15 1 -33 -57 -83 0.7 121721 1.5 -32-54-78 1 172429 2 -29-49-72 1.2 202835 2.5 -25-44-64 1.5 233442 2.7 -23-41-61 1.7 263747 3 -20-37-56 2 284253 3.2 -18-34-52 2.2 304557 3.5 -14-29-46 2.5 324863 3.7 -12-26-42 2.7 335067 4 -8-20-36 3 345371 4.2 -5-16-32 3.5 355677 4.5 0-11-25 4 355782 4.7 -6-20 4.5 355884 5 0-13 559855.2 -8 5.5 87 5.5 0 -100 -80 -60 -40 -20 0 20 40 60 80 100 - 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 output voltage (v) output current (ma) min typ max 70 w load the data in this table represents nominal characterization data only.
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t november 1998 11.20.98 7 )6 )lyh3//&orfn*hqhudwru,& ,62 6.0 package information table 8: 16-pin soic (0.150") package dimensions dimensions inches millimeters min. max. min. max. a 0.061 0.068 1.55 1.73 a1 0.004 0.0098 0.102 0.249 a2 0.055 0.061 1.40 1.55 b 0.013 0.019 0.33 0.49 c 0.0075 0.0098 0.191 0.249 d 0.386 0.393 9.80 9.98 e 0.150 0.157 3.81 3.99 e 0.050 bsc 1.27 bsc h 0.230 0.244 5.84 6.20 h 0.010 0.016 0.25 0.41 l 0.016 0.035 0.41 0.89 q 0 8 0 8 be d a 1 seating plane h e 16 1 all radii: 0.005" to 0.01" base plane a 2 c l q 7 typ. h x 45 a
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t r table 9: 16-pin soic (0.150") package characteristics parameter symbol conditions/description typ. units thermal impedance, junction to free-air q ja air flow = 0 m/s 109 c/w corner lead 4.0 lead inductance, self l 11 center lead 3.0 nh lead inductance, mutual l 12 any lead to any adjacent lead 0.4 nh lead capacitance, bulk c 11 any lead to v ss 0.5 pf
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t nove m ber 1998 11.20.98 8 )6 )lyh3//&orfn*hqhudwru,& ,62 7. 0 ordering inf o rmation order i ng co d e d evi c e nu m b e r font p a c k a ge ty p e oper a t i n g tempe r a ture r a nge s h i p pi n g conf i gu r a t i on 11117-002 fs6017 -0 2 16-pin (0.150) soic (s m all ou t lin e p a c k age) 0 c to 7 0 c (c o m m e r cial) tape-and-reel copyright ? 1998 a merican m icros y ste m s, inc. devices sold b y a m i a r e covered b y the warran t y an d pa t en t i n de m ni f icatio n pr o visi o ns a p pea r ing in its t er m s of sale on l y . ami m a k es no warran t y , express, sta t uto r y i m plied or b y descrip t io n , rega r ding t h e in f or m ation set f orth her e i n or regarding t he f ree d om of the describe d d e vices f rom patent in f ringe m ent. ami m a k es n o warran t y of m erchantabili t y or f itness f or a n y p urposes. am i r eserves t he righ t to d iscon t in u e pr o ductio n and c h an g e spe c i f icati o ns and prices a t a n y ti m e an d with o ut n otic e . a mis products are i n te n ded f or use in c o m m e rcial a p plications . ap p lic a ti o ns req u irin g ex- ten d e d t e m peratur e ran g e , u nusu a l e nviron m ent a l re q uire m ents, or h igh r e lia b ili t y a p plica t ions, such as m ilita r y , m edi- ca l li f e-suppor t or li f e-sustai n ing e q u ip m ent, are s p eci f ical l y not reco m m ende d with o u t ad d i t io n a l processing b y a mi f or such ap p lica t i o ns. a m e r i can m icro s y st e ms, i n c., 2 300 buc k skin r d ., p o catell o , i d 83 2 01 , ( 2 08) 2 3 3-46 9 0 , f a x ( 2 08) 2 34-679 6 , www a dd r ess: http://w w w.amis.com e-mail: tgp@amis.com
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